Hariprakash Govindarajalu

CTO, GradsKey

  • National Institute of Technology, Tiruchirappalli
    M.Tech Computer Science
    1993 - 1994



Results-oriented and multi-skilled Architect with strong technical and innovative skills offering 26+ years of rich experience in leading Processor diagnostics and Server Operating system sustaining organizations to world class performance. Proven excellence in setting up and managing successful R&D teams. Strong architecting expertise and experience in system software level and enterprise application level.


Chief Technology Officer
Dec 2019 - Present
Responsible for setting and driving tech architectural direction for GradsKey and developing world-class technical talent.

Chief Technology Officer
Logic Research Labs
Jun 2017 - Present
Kumbakonam Area, India
Working on Bootstrapping Startups, building their very first prototypes at LRL. Developing new technologies. New products research and development.

Staff Engineer II - Kernel/Hardware Platform Engineer
Feb 2011 - Jun 2017
Palo Alto, CA
Work on legacy processor enablement of VMware ESX kernel. Developing diagnosing tools for debugging. Root causing and fixing complex Kernel/Hardware issue. Diagnosing x86 processor/hardware faults. Recommending serviceability enhancements to vmkernel. Filed Patent and Trade Secret on hardware faults.

Chief Architect
Logic Research Labs
Jun 2006 - Feb 2011
Kumbakonam Area, India
Chief Architect for Enterprise software solutions. Significant contribution to high & low level design details, planning, scheduling, resource allocation, and resolving critical issues in the product development process and in production environments. Architected around 25 products using LAMP and Java EE/EJB Involved in all phases software development life cycle of various Enterprise applications. Tuned software engineering approaches suited for R&D environment, successfully applied prototyping approach, pair programming model and agile software development methodologies. Designed, developed and delivered a number of Enterprise application solutions – Yahoo Mashups, EMR, HMIS, and ERP using Java EE, EJB 3, JPA, XML-RPC, REST, Ajax and LAMP platforms. Inception and setting up of R&D department for software development in Logic Research Labs. Worked on hiring talents, motivating research and provided an excellent platform for fostering research and developing of enterprise software products. Efficiently managed R&D and product development teams and envisioned roadmap of products that are profitable to the company.

CPU Diagnostics Architect
Sun Microsystems
2003 - 2006

Pioneered the idea of using full-system simulator (Simics), that expedited writing CPU diagnostic programs prior to tape-out, contributing to significant reduction in development time of Niagara - 8 cores CMP diagnostics for a new platform..

Invented and developed hexadecimal digital root generator/checker circuits for arithmetic error detection in integer unit. US patent #7,412,475

Architect and developer of Level-3 cache diagnostics for dual core processor (Panther), incorporated into Sun Validation Test suite.

Invented the on-the-fly I-Cache testing method using side-effect fill, which triggered many novel techniques for I-Cache and TLB testing. US Patent filed.

Developed an error-injection framework for coverage analysis of CPU diagnostics.

Significantly improved and contributed to CPU diagnostics routines of Sun Validation Test Suite – a product used to screen Sun Enterprise server class machines.

Planning and working with architects, other engineering teams and cross functional departments in defining the road map of CPU diagnostics at Sun Microsystems.

Senior Engineering Manager
Sun Microsystems
Dec 2006 - Aug 2011

Responsible for the Design & development of the user level Application based engines to verify the HW and SW product performance, availability and stability.

Includes at the SW Level: Linux/Solaris OS kernel level, TCP/IP networking stack, IB stack, File system, and other sub-component verification; at the HW level: Platform Server components.

Sr. Engineer Kernel Group
Sun Microsystems
1997 – 2003

Invented PAST (Power After Self-Test framework) for periodic health-checking of processors in Sun Enterprise class server machines - US patent #7,509,533

Created CPU diagnostic test suite used for screening SPARC processors at Texas Instruments. Developed IU/FPU register file/path diagnostics that are incorporated into Sun Validation Test Suit.

Designed and developed a live kernel instrumentation framework useful for collecting pertinent kernel execution trace data. Used as internal kernel tool for hot patching.

Resolved complex problems like handling of NaN operands in hardware by nucleus code which avoided replacement of 300 odd Sun Microsystems mid-range server machines from the customer.

Resolved more than 100 critical escalations in Solaris Kernel. Involved in root-cause-analysis of various CPU failures, and presentation of RCA to high profile customers.

Part of platform dependent Solaris kernel sustaining team, specifically handling MMU, Open Boot firmware, Kernel and Nucleus code. Fixed and released Solaris kernel patches.

Staff Engineer
Sun Microsystems
Jul 1997 - Feb 2002

Architected & developed an innovative on-site production server system diagnostic test solution for high available systems.

Designed & developed on-the fly device drivers/kernel modules instrumentation framework to add on-demand functional enhancements, performance tuning and debugging. With this framework, many customer's performance problems got resolved, and few features were added to the demanding high profile customers, resulted in better customer satisfaction.

Lead the team of engineers for quality platform dependent kernel/OS sustaining.

Managed high profile (banking and telecom) customer data center technologies, and helped them improve their performance significantly, making positive impact in their business. This created new revenue opportunities for sales through reference.

Provided cross-team mentorship and technical training on the new engineering products.


National Institute of Technology, Tiruchirappalli
M.Tech Computer Science, Advanced Computer Architecture
1993 - 1994

Kongu Engineering College
B.E Computer Science & Engineering, Bhartathiyar University - 4th Rank
1988 - 1992

Professional Achievements

10  Publications

Testing CPU stability using Multi-precision Arithmetic by calculating n digits of Pi on International Mathematical Conference on Number Theory and Modular forms
Srinivasa Ramanujan Centre, SASTRA University, Kumbakonam, India.

Coverage analysis of Borwein-Borwein quadratic convergence Pi algorithm for FPU diagnostics on International Mathematical Conference on Number Theory and Modular forms
Srinivasa Ramanujan Centre, SASTRA University, Kumbakonam, India.

Error Detecting Arithmetic Circuits using Hexadecimal digital roots at 6th Annual Test
Sun conference, Menlopark, CA, US
Apr 2003

PAST: Power After Self Test - a periodic CPU module health-checker in a multiprocessor environment at 5th Annual Test
Sun conference, Menlopark, CA, US
Apr 2002

Hardware compilation pipeline for High-performance Java processor at Java in Embedded systems workshop on International Conference on Architecture
Computing systems ARCS, Karlsruhe, Germany
Apr 2002

Bytecode traces: Exploiting Java-ILP at Java in Embedded systems workshop on International Conference on Architecture on Computing systems ARCS 2002
Computing systems ARCS, Karlsruhe, Germany
Apr 2002

Exploiting Java-ILP on a Simultaneous Multi-Trace Instruction Issue (SMTI) Processor Proceedings of the 17th International Symposium on Parallel and Distributed Processing
International Symposium on Parallel and Distributed Processing

DSTRIDE: Data-cache-miss-address-based stride prefetching scheme for multimedia processors
6th Australasian computer systems architecture conference ACSAC
Jan 2001

PARDISC: A Cost-effective model for parallel and Distributed Computing at IEEE and ACM
3rd International Conference on High-Performance Computing (HiPC)
Dec 1996

Iterative Data Selection Algorithm for Psychiatry Electronic Medical Records
Technologies Driving e-health, e-education, e-governance, Networking, Automation, and Cloud Computing” 19th Annual Symposium of IEEE, Bangalore
Dec 2010
Issued Dec 28, 2017
us 10331546
An automated end-to-end analysis of customer service requests is disclosed. A core dump is received, wherein the core dump corresponds to a customer service request regarding a crash of a computer system. A processor automatically analyzes the core dump to determine if a pcpu lockup of the computer system is due to a software issue. Provided the pcpu lockup of the computer system is due to the software issue, the processor determines which thread is a culprit thread responsible for the pcpu lockup of the computer system.
See Patent

Detecting x86 cpu register corruption from kernel crash dumps
Issued Mar 26, 2015
us 9552250
When an operating system or application fails, a function containing the instruction that failed along with the register set of the CPU at the failure is recorded. The function is analyzed into its basic blocks. The failing instruction, the failing basic block, the definitions that reach the failing instruction, and the CPU register set at the failure provide information to determine whether the failure was caused by hardware or software.
See Patent

Methods and apparatus for testing functionality of processing devices by isolation and testing
Issued Mar 24, 2009
us 7,509,533
A computerized device having a first processing device, a second processing device, and an interconnection mechanism allowing communication between the first and second processing devices, provides a mechanism for testing a processing device by performing the isolation and testing operations of operating the first processing device in a normal processing mode and transitioning the first processing device from the normal processing mode to an isolated processing mode. The device performs a test process on the first processing device while in isolated processing mode to test functional portions of the first processing device. If operation of the test process produces an error in a functional portion of the first processing device, the test process notifies a control process on a second processing device of the error in the functional portion of the first processing device in which the test process produced an error. If operation of the test process does not produce an error in the functional portions of the first processing device, the device transitions the first processing device from the isolated processing mode back to the normal processing mode upon completion of the test process. The process can be repeated periodically on all processors in a device at an interval that is less than an average mean time between failures of the processing devices.
See Patent

Error detecting arithmetic circuits using hexadecimal digital roots
Issued Dec 8, 2008
us 7,412,475
Embodiments of the invention are directed to circuits and techniques for computer processor register integrity checking employing digital roots, and hexadecimal digital roots (HDRs) in particular, to validate the results of arithmetic operations and register moves. These circuits thus provide extra confidence that register operations were correctly executed. A hexadecimal digital root is computed for the result of each register computation and compared to the results of the same computation performed on the HDRs of the operands. The hexadecimal digital root approach may be simply implemented with standard combinatoric logic. Validation is accomplished in a single clock cycle so that there is no added system delay or latency. The circuits and methods described herein have comparatively little impact on processor real estate.
See Patent
Recipient of Sun Microsystems Quality Engineering Excellence Award.

Received Performance Excellence awards in Sun Microsystems.

Recipient of Silver Jubilee Distinguished Alumni Award from Kongu Engineering College