Results-oriented and multi-skilled Architect with strong technical and innovative skills offering 26+ years of rich experience in leading Processor diagnostics and Server Operating system sustaining organizations to world class performance. Proven excellence in setting up and managing successful R&D teams. Strong architecting expertise and experience in system software level and enterprise application level.
Pioneered the idea of using full-system simulator (Simics), that expedited writing CPU diagnostic programs prior to tape-out, contributing to significant reduction in development time of Niagara - 8 cores CMP diagnostics for a new platform..
Invented and developed hexadecimal digital root generator/checker circuits for arithmetic error detection in integer unit. US patent #7,412,475
Architect and developer of Level-3 cache diagnostics for dual core processor (Panther), incorporated into Sun Validation Test suite.
Invented the on-the-fly I-Cache testing method using side-effect fill, which triggered many novel techniques for I-Cache and TLB testing. US Patent filed.
Developed an error-injection framework for coverage analysis of CPU diagnostics.
Significantly improved and contributed to CPU diagnostics routines of Sun Validation Test Suite – a product used to screen Sun Enterprise server class machines.
Planning and working with architects, other engineering teams and cross functional departments in defining the road map of CPU diagnostics at Sun Microsystems.
Responsible for the Design & development of the user level Application based engines to verify the HW and SW product performance, availability and stability.
Includes at the SW Level: Linux/Solaris OS kernel level, TCP/IP networking stack, IB stack, File system, and other sub-component verification; at the HW level: Platform Server components.
Invented PAST (Power After Self-Test framework) for periodic health-checking of processors in Sun Enterprise class server machines - US patent #7,509,533
Created CPU diagnostic test suite used for screening SPARC processors at Texas Instruments. Developed IU/FPU register file/path diagnostics that are incorporated into Sun Validation Test Suit.
Designed and developed a live kernel instrumentation framework useful for collecting pertinent kernel execution trace data. Used as internal kernel tool for hot patching.
Resolved complex problems like handling of NaN operands in hardware by nucleus code which avoided replacement of 300 odd Sun Microsystems mid-range server machines from the customer.
Resolved more than 100 critical escalations in Solaris Kernel. Involved in root-cause-analysis of various CPU failures, and presentation of RCA to high profile customers.
Part of platform dependent Solaris kernel sustaining team, specifically handling MMU, Open Boot firmware, Kernel and Nucleus code. Fixed and released Solaris kernel patches.
Architected & developed an innovative on-site production server system diagnostic test solution for high available systems.
Designed & developed on-the fly device drivers/kernel modules instrumentation framework to add on-demand functional enhancements, performance tuning and debugging. With this framework, many customer's performance problems got resolved, and few features were added to the demanding high profile customers, resulted in better customer satisfaction.
Lead the team of engineers for quality platform dependent kernel/OS sustaining.
Managed high profile (banking and telecom) customer data center technologies, and helped them improve their performance significantly, making positive impact in their business. This created new revenue opportunities for sales through reference.
Provided cross-team mentorship and technical training on the new engineering products.